Università degli Studi di Napoli "Parthenope"

Teaching schedule

Academic year: 
2018/2019
Belonging course: 
Course of Bachelor's Degree Programme on COMPUTER SCIENCE
Disciplinary sector: 
INFORMATICS (INF/01)
Language: 
Italian
Credits: 
12
Year of study: 
1
Teachers: 
SCAFURI Umberto
Cycle: 
First Semester
Hours of front activity: 
96

Language

Italian

Course description

The objective of the course of “Computer Architecture and Computer Architecture Laboratory” is to illustrate the basic aspects of modern electronic computers, as well as to handle and use, during the preposed laboratory activities, the basic concepts for their efficient programming in low-level languages, as machine language and Assembly. To this aim, after a careful coverage of the Boole Algebra (used in laboratory for the Synthesis of sequential and Combinatorial logical Networks), of the binary representation as well as the binary arithmetic, it illustrates in detail, as fundamental elements in the architecture of the information systems, the functional/physic scheme of the CPU, the memory and the I/O subsystem.During the course particular attention is devoted to the development of the Assembly code that, developed by the students as laboratoty activity, in addition to clarify them the effective principle of processor working, explains in detail the task, the interconnection and the interaction among the different basic units of a computer.
Knowledge and comprehension capability: the didactc acitivities carried out during the course aim to provide the student, hypothesized to be endowed with a poor or nonexistent informatic qualification, a good knowledge of both characteristic aspects of binary systems as the functional principles they are based on.
Capability to apply knowledge and comprehension: the theoretical study and the development of the various theoretical/practical tests effected by the sudent during the course, aim to provide him with a correct vision of the computers, with the aim to evidence both the potentialities and the limits they present in the solution of real problems.
Autonomy of judgement: the student must be able to write programs in Assembly that allow representing and elaborating effectively in binary real problems of different nature.
Communicative abilities: the student must be able to partecipate actively in working groups in design/implemetation/documentation of Assembly applications. To this aim, the knowledge acquired during the course of the correct technical terminology used in the informatic area.
Comprehension capability: the treated topics binary representation/elaboration, logical networks, processors as well as the logical sequence to pass from the ones to the others, provides the student with both a global vision and that of three different areas. The capability of comprehending to the best the possible advantages/disandvantages, that possible technological proposals can bring to a processor, allows the student the capability to autonomously bring himself up to date from the different sources present in Internet.

Prerequisites

None.

Syllabus

Genral organization of a computer: hardware and software. Application software and basic software. The on Neumann model. Functional principles of a computer. Boole algebra. Boolean functions and truth tables. Logical gates: combinatorial networks. Combinatorial network design. Half adder and full adder. Karnaugh maps. Finite state automa. Sequential networks. Memory elements. Structure and functioning of a sequential network. Flip-flop. Registers.
Representation and data encoding: information encoding. Redundant codes. Error Detection and correction, expansion codes. Coder and decoder. Addressable multiplexer and demultiplexer. The positional numbering system. The binary numbering. The decimal numbering. Natural number representation. Relative number representation. Base complements. Decreased complements. Representation of fixed-point and floating-point real numbers. Computer aritmethic. Principle scheme of a computer.
Organization and operating principles of a computer based on von Neumann model. Principle scheme of a computer: elements of the central unit (control unit, machine registers (PC, MA, MB, IR, SR - and ALU). The processor cycle. Processor data-path. Microprogrammed architectures. Architectural elements of a microprogrammed processor. Microprogramme. Machine and micromachine instructions. Function and organization of the central memory. Processor-memory interface. Synchronous ansd asynchronous techniques. Interrupt phase in the processor cycle. Interrupt system.
Memory: characteristic parameters of a memory. Memory hierarchy. RAM and ROM memories. Cache memory. Bascking store (CD, HD, Floppy, Tape). Internal architecture of a memory module. Linear selection scheme and semi-selection. Composition of memory modules. Serial and parallel linking. Verification techniques of data integrity. Interleaving memory.
Interface processor-I/O devices: architectural models. Sinlge bus structure. Double bus structure. DMA structure. Programming models: memory mapped I/O, I/O with special instructions. CISC, RISC and VLIW processors: basic and fundamental concepts. Instruction set, orthogonal organization and load/store, CISC and RISC machines. Didactic example: registers, instruction set, pseudo instructions and Assembly language. Microprogramme examples.
Laboratory activity, Assembly language: introduction to assembly language. Elementary operating codes. Instruction format. Addressing modality. Subroutine. Mention to the linkage and parameter transfer problems.
Assembly program development for the 6800 processor. Calls: 6800 processor programming model, instruction format and operating codes. Addressing modality. Linkage and parameter transfer. 6800 processor Assembly. Development of assembly programs for the 6800 processor. Assembler, linker, loader, libraries and run-time supports.
Close examination: DMA access, vectorized interrupts. Virtual memory (segmentation and pagination) and harware support for the address translation. Protection mechanisms and Trap. Associative cache and direct correposndence memories. Pipelining and caching techniques. Superscalar cache.
Calls to multicore and manycore modern systems: architectural characteristics and distinctive aspects.

Teaching Methods

Textbooks

W. STALLINGS: “Architettura e organizzazione dei calcolatori (progetto e prestazioni)”, Pearson Italia..
G. BUCCI: “Architettura dei calcolatori elettronici: fondamenti”, Mc Graw-Hill Italia.

The didactic material (lecture notes, exercises, examination program, etc, in pdf format and potential multimedia presentations in flash format) is available trough the e-learning Service of the Sciences and Technologies Faculty at the Web address:
http://e-scienzeetecnologie.uniparthenope.it/

Learning assessment

The assessment objective consists in quantifying, for each student, the learning level acquired with respect to the contents listed in the program of ‘Computer Architecture and Laboratory of Computer Architecture’ above reported. The assessment procedure consists of an oral examination (50% of the vote) inherent to the explained contents of the program, and of a written examination in which the student is required to solve queries related to the logical networks synthesis (20% of the vote) and the development of Assembler 68K code (30% of the vote). Obviously, the complexity of the different queries proposed in the written examination is of the same difficulty level as the assisted practices envisaged as laboratory activity.
For a positive assessment result, the positive outcomes of both the examinations are needed: written examination (logical networks plus Assembler code) and oral examination.

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