Università degli Studi di Napoli "Parthenope"

Teaching schedule

Academic year: 
2016/2017
Belonging course: 
Course of Bachelor's Degree Programme on COMPUTER SCIENCE, BIOMEDICAL AND TELECOMMUNICATIONS ENGINEERING
Disciplinary sector: 
INFORMATION PROCESSING SYSTEMS (ING-INF/05)
Credits: 
12
Year of study: 
3
Cycle: 
Second semester
Hours of front activity: 
96

Language

Italian

Course description

Objectives of the course in terms of knowledge and abilities are:
- Knowledge and understanding: i) binary logic ii) internal organization of microprocessor based systems; iii) internal organization of microprocessor based systems; iv) analysis and design of embedded systems.

- Applying knowledge and understanding: i) analysis and design of logic circuits: combinational and sequential; ii) design and programming of microprocessor based systems; iii) design and implementation of embedded systems.

- Making judgements: i) evaluation and comparison of logical function implementations; evaluation and comparison of microprocessor based system.

- Learning skills: i) consulting reference literature; ii) searching and consulting online databases and repositories.

- Communication skills: i) mastery of the jargon with respect to the course topics; ii) team working

Prerequisites

Knowledge of Computer Programming and Digital Circuits is beneficial.

Syllabus

Logic Circuits (2 CFU, 16 h): Basic Logic Functions; Synthesis of Logic Functions; Minimization of Logic Expressions; Flip-Flops; Registers and Shift Register; Counters; Decoders; Multiplexers; Sequential Circuits. Organization of a computer system (1 CFU, 8 h): Computer types; functional units; basic operational concepts; Number Representation and Arithmetic Operations; Software; The Assembly process, two pass assembler; Loading and Executing Object Programs; The Linker; Libraries; The Compiler; The Debugger Performance; Multriprocessors and Multicomputer; Historical Perspective. Basic Processing Unit (1 CFU, 8 h): Instruction Execution; Hardware components; Instruction Fetch and Execution; Control Signals; Hardwired and Microprogrammed Control. Instruction Set Architecture (1 CFU, 8 h): Memory locations and Addresses; Memory Operations; Instruction and Instruction Sequencing; Addressing Modes; Assembly Language; Stacks; Subroutines; Additional Instructions (Logic/Shift-Rotate/Multiplication and Division). CISC Instruction set and RISC Style (3 CFU, 24 h): ARM, Motorola and Intel case studies. Basic INPUT/OUTPUT (1 CFU, 8 h): I/O Device Interface; Program Controlled I/O, Interrupts; ARM, Motorola and Intel case studies. The Memory System (1 CFU, 8 h): Basic Concepts; Types of Memories; Memory Hierarchy; Direct Memory Access; Cache Memories; Performance Considerations; Virtual Memory; Memory Management Requirements; Secondary Storage. Pipelining (1 CFU, 8 h): Introduction to pipeline organization and Data Dependencies. Embedded Systems (1 CFU, 16 h): Example of Embedded Systems; Microcontroller Chips for Embedded Applications; Organization of a Microcontroller; Microcontroller Families, Design Issues. System-on-a-Chip.

Logic Circuits (2 CFU, 16 h), Organization of a computer system (1 CFU, 8 h), Basic Processing Unit (1 CFU, 8 h), Instruction Set Architecture (1 CFU, 8 h), ). CISC Instruction set and RISC Style (3 CFU, 24 h), Basic INPUT/OUTPUT (1 CFU, 8 h), The Memory System (1 CFU, 8 h), Pipelining (1 CFU, 8 h), Embedded Systems (1 CFU, 16 h).

Teaching Methods

Classes will be given in a multimedia room and will alternate theoretical aspects and their applications. Team building and working will be encouraged. Traditional classroom lessons will be combined with online digital contents and lessons provided as e-learning. E-learning study material is provided in Italian.

Textbooks

Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization and Embedded Systems,Sixth Edition, McGraw-Hill Higher Education, 2011, ISBN-10: 0073380652.

Learning assessment

Homework will be continuously proposed to enable auto-evaluation of students’ knowledge.
The final assessment will be performed through a multichoice test and the proposal of a simple problem to be solved in assembly for one of the three architectures presented during the course). A final discussion (only for those who pass the practical assessment), will allow to evaluate the mastery of the jargon with respect to the course topics and the ability to elaborate the knowledge gathered in the course.

For non-italian students, final exam can be in English.

More information

Attending classes is strongly suggested E-learning contents will be provided at the edi.uniparthenope.it address. At the same platform free material produced by the instructor will be made available.

Additional learning material will be provided in English.

Professors are fluent in English and are available to interact with students in English, also during the examination.

Office hours: Monday 10 a.m. - 1 p.m.